-------------------------------------------------------------------------------
--
-- Title       : No Title
-- Design      : tests
-- Author      : aldec
-- Company     : Microsoft
--
-------------------------------------------------------------------------------
--
-- File        : C:\Users\vincenti\Desktop\testworkspace\wkspace\tests\compile\test.vhd
-- Generated   : 02/10/15 10:42:15
-- From        : C:\Users\vincenti\Desktop\testworkspace\wkspace\tests\src\test.asf
-- By          : FSM2VHDL ver. 5.0.7.2
--
-------------------------------------------------------------------------------
--
-- Description : 
--
-------------------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

entity test is 
	port (
		a: in STD_LOGIC;
		clk: in STD_LOGIC;
		enable: in STD_LOGIC;
		reset: in STD_LOGIC;
		z: out STD_LOGIC);
end test;

architecture test_arch of test is

-- diagram signals declarations
signal delay_counter_Sreg0: INTEGER range 0 to 3;
signal sl_enable: STD_LOGIC;

-- SYMBOLIC ENCODED state machine: Master Machine
type Master Machine_type is (
    S2_S5, S2_S6, S1, S3, S4
);
-- attribute ENUM_ENCODING of Master Machine_type: type is ... -- enum_encoding attribute is not supported for symbolic encoding

signal Master Machine, NextState_Master Machine: Master Machine_type;

-- SYMBOLIC ENCODED state machine: Sreg0
type Sreg0_type is (
    S7, S8, D1_DS1
);
-- attribute ENUM_ENCODING of Sreg0_type: type is ... -- enum_encoding attribute is not supported for symbolic encoding

signal Sreg0, NextState_Sreg0: Sreg0_type;

-- Declarations of pre-registered internal signals
signal int_z, next_z: STD_LOGIC;
signal next_delay_counter_Sreg0: INTEGER range 0 to 3;

begin


----------------------------------------------------------------------
-- Machine: Master Machine
----------------------------------------------------------------------
------------------------------------
-- Next State Logic (combinatorial)
------------------------------------
Master Machine_NextState: process (a, int_z, Master Machine)
begin
	NextState_Master Machine <= Master Machine;
	-- Set default values for outputs and signals
	next_z <= int_z;
	case Master Machine is
		when S1 =>
			next_z <= '0';
			if a='1' then
				NextState_Master Machine <= S2_S5;
			end if;
		when S3 =>
			next_z <= '1';
			sl_enable <= '1';
			if a='1' then
				NextState_Master Machine <= S4;
			end if;
		when S4 =>
			next_z <= '0';
			if a='1' then
				NextState_Master Machine <= S1;
			end if;
		when S2_S5 =>
			NextState_Master Machine <= S2_S6;
		when S2_S6 =>
			if a='1' then
				NextState_Master Machine <= S3;
			end if;
--vhdl_cover_off
		when others =>
			null;
--vhdl_cover_on
	end case;
end process;

------------------------------------
-- Current State Logic (sequential)
------------------------------------
Master Machine_CurrentState: process (clk)
begin
	if rising_edge(clk) then
		if reset='1' then
			Master Machine <= S1;
		else
			if enable = '1' then
				Master Machine <= NextState_Master Machine;
			end if;
		end if;
	end if;
end process;

------------------------------------
-- Registered Outputs Logic
------------------------------------
Master Machine_RegOutput: process (clk)
begin
	if rising_edge(clk) then
		if reset='1' then
			int_z <= '0';
		else
			if enable = '1' then
				int_z <= next_z;
			end if;
		end if;
	end if;
end process;

-- Copy temporary signals to target output ports
z <= int_z;


----------------------------------------------------------------------
-- Machine: Sreg0
----------------------------------------------------------------------
------------------------------------
-- Next State Logic (combinatorial)
------------------------------------
Sreg0_NextState: process (delay_counter_Sreg0, Sreg0)
begin
	NextState_Sreg0 <= Sreg0;
	-- Set default values for outputs and signals
	next_delay_counter_Sreg0 <= delay_counter_Sreg0;
	case Sreg0 is
		when S7 =>
			NextState_Sreg0 <= D1_DS1;
			next_delay_counter_Sreg0 <= 3 - 1;
		when S8 =>
			NextState_Sreg0 <= S7;
		when D1_DS1 =>
			if delay_counter_Sreg0 = 0 then
				NextState_Sreg0 <= S8;
			else
				NextState_Sreg0 <= D1_DS1;
				if delay_counter_Sreg0 /= 0 then next_delay_counter_Sreg0 <= delay_counter_Sreg0 - 1;
				end if;
			end if;
--vhdl_cover_off
		when others =>
			null;
--vhdl_cover_on
	end case;
end process;

------------------------------------
-- Current State Logic (sequential)
------------------------------------
Sreg0_CurrentState: process (clk)
begin
	if rising_edge(clk) then
		if reset='1' then
			Sreg0 <= S7;
		else
			if sl_enable = '1' then
				Sreg0 <= NextState_Sreg0;
			end if;
		end if;
	end if;
end process;

------------------------------------
-- Registered Outputs Logic
------------------------------------
Sreg0_RegOutput: process (clk)
begin
	if rising_edge(clk) then
		if reset='1' then
		else
			if sl_enable = '1' then
				delay_counter_Sreg0 <= next_delay_counter_Sreg0;
			end if;
		end if;
	end if;
end process;

end test_arch;
